1) Field of the Invention
The present invention relates to a double super heterodyne tuner to be used in the television receiver and the like.
2) Description of the Prior Art
A conventional double super heterodyne tuner is described below.
FIG. 3 is a block diagram showing the constitution of a conventional double super heterodyne tuner. In FIG. 3, an RF signal entered from an antenna is fed into an RF amplifier 2 through an input terminal 1 to be selected and amplified, and is mixed with a signal issued from a first local oscillator 4 in a first mixer 3, and is converted into a first intermediate frequency signal. Since the first intermediate frequency signal is generally set at a frequency higher than the RF signal in a receiving band, the portion up to conversion into the first intermediate frequency signal is called an upconverter 21. The first intermediate frequency is selected and amplified in a first intermediate frequency amplifier 8, and given to a second mixer 9, where it is mixed with a signal from a second local oscillator 10 to be converted into a second intermediate frequency signal. The signal from the second mixer 9 is given to a second intermediate frequency amplifier 13, and is amplified and issued to an output terminal 14. The second intermediate frequency signal given to the output terminal 14 is generally set at a frequency lower than the RF signal in a receiving band, and hence the portion of converting the first intermediate frequency signal into the second intermediate frequency signal is called a downconverter 22.
The first local oscillator 4 is composed of a voltage controlled oscillator, and the output of the first local oscillator 4 is divided in a predivider 5 at a specific frequency dividing ratio (for example, 1/256), and the divided frequency signal is output through a first local oscillation dividing output terminal 6. The output signal is connected to a PLL frequency synthesizer at the set side composed of a variable divider, a reference oscillator, a phase comparator, and a low pass filter, a controlled voltage fixed at an arbitrary local oscillation frequency by the station selection data given to the variable divider is generated, and this voltage is supplied into a first local oscillation controlled voltage input terminal 7, and is controlled to a desired local oscillation frequency.
The second local oscillator 10 is also composed of a voltage controlled oscillator, and as the output of the second local oscillator 10, the oscillation frequency signal itself is issued from a second local oscillation output terminal 11. This output is similarly connected to a PLL frequency synthesizer, and the local oscillation frequency is controlled.
Prior art of this type is disclosed, for example, in the Japanese Laid-open Patent Publication Hei. 2-217024.